Fix: CW Keying recommendS YOU COMPLETE A CW KEYING fix

Some µBitx builders have found that their straight key or their paddle doesn’t always work reliably with the existing arduino analogue port approach.   Others have not noticed the issue.   A single analogue input port (A6) is used in combination with three different values of resistance to key a “dit”, a “dah” and a “straight key” depress.

The problem appears to be a combination of timing delays built into the software and “dirty” contacts on keys (paddles and straight keys).   Dirty contacts mean that the resistance may not be as expected by the software, or the resistance may change over a few microseconds or milliseconds after depressing the key.

There are several different approaches to fixing the keying issue at present:

  • Apply a software update (Ian KD8CEC)
  • Hardware adjustment to change out 2.2k resistor and make minor amendment to the software (John AD0RW)
  • Hardware solution to force zero resistance
  • Hardware and software solution to shift keying off the analogue port to two digital I/O ports PREFERRED APPROACH
Software update (Ian Lee KD8CEC)

Ian Lee has released a bug fix and software upgrade (to provide CAT control for the µBitx).   This is a software update only.  It is easy to return your µBitx  to its original state if it turns out you don’t appreciate Ian’s software enhancements, by re-installing the manufacturer’s sketch.

A  Hardware Solution (John AD0RW)   

John incorporated the keyer code from W0EB and W2CTX into his personal software build, but he was determined to save the last analog input for S Meter or Power Output metering. 

He kept the single input that detects four different levels (He left out the input for a straight key). Some of the errors he  and others have reported with the single input line seemed to be consistent with the ADC deciding the state was “both” instead of “dit”, for example an ‘I’ becoming an ‘N’ while the dit paddle is held closed. Looking at the nominal voltage levels with the provided resistors, John saw that there was only around 0.22 volts between the “dit” and “both” levels (1.60 vs 1.38 V). On the other hand, there is 1.8 volts between “dit” and “dah”. Errors due to fluctuations would be much more likely between “dit” and “both”.

Hoping to improve the situation, he did a little numerical study of the divider circuit. It turned out that there is really no area in the 2D “space” of possible resistor values that gives an ideal result (large equal intervals between both pairs of levels), but it is possible at least to increase the dit-both spacing significantly, at the expense of the dit-dah spacing. In the end he replaced the 2.2k resistor with a 5.1k one. Now the nominal levels are 3.4 V for “dah”, 2.6 V for “dit”, and 2.1 V for “both”. I made an educated estimate of what the boundary ADC values should be and put them into my customised paddle-latch function.

John has found the results so far are favourable.